1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to sense amplifier enable drivers.
2. Description of the Related Art
Typically, modern semiconductor memories (whether embodied in a memory integrated circuit or incorporated in larger designs, e.g., as cache memory of a processor integrated circuit) employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. Such differential amplifier and sensing circuits are commonly known as sense amplifiers (sense amps) and a wide variety of sense amplifier designs are known in the art, including current sensing and voltage sensing variations.
Generally, when designing sense amplifiers, great care is taken to optimize timing and balance. Typically, a signal such as a sense amplifier enable (SE) is used to time sense amplifier operation. For example, one state of an SE signal is often used to equalize sense amplifier nodes for a period that allows differential bit-lines to develop sufficient voltage differential to support sensing. Once the differential bit-lines have developed sufficient differential, SE is transitioned to cause the sense amplifier to actually sense the developed differential.
Generally, if the equalization period defined by SE transitions is too short, then the bit-lines may not develop sufficient differential for the sense amplifier to correctly sense the data being read from an addressed memory cell. On the other hand, if too much time is allowed for SE, then access time of the memory circuit is increased and achievable operating frequency (or at least memory access bandwidth) may be reduced. Therefore, in high-speed designs, the SE signal delay path is designed to deliver the SE transition at just the right time to ensure that correct data is being read, while aiming to minimize shortest cycle time.
In some typical sense amplifier designs, the equalization operation and the sensing operation have different requirements. For example, it may be preferable to limit the slope of the SE signal to make the sensing operation more reliable, e.g., by slowing the rate of discharging a common node to reduce false switching inside the sense amplifier but maintaining the rate of discharging the common node so that it is faster than the rate of discharging a bit-line. In addition, the equalization operation is preferably disabled prior to the sensing operation in order to allow a signal to develop. One technique for generating control signals having these different timing requirements uses two separate drivers. However, if two separate drivers are used, a fixed relationship between the signals becomes difficult to maintain due to circuit matching discrepancies, e.g., device mismatches produced by process variations. Accordingly, new techniques are desired to address generation of sense amplifier control signals.